The Verilog code below contains a description of a system consisting of two clients, a shared resource, and an arbiter. Everything is already designed (including the testbench) with the exception of the arbiter. The shared resource is a FIFO (first-in, first-out) buffer. The clients simply generate random requests to store randomly generate data in the FIFO. They only try to write data to the FIFO if it is not full. A control circuit pops data from the FIFO when no client is trying to write, provided the FIFO is not empty.
Your task is to design the arbiter following the example in the sequential.pdf
slide deck. The difference with respect to that example is that your arbiter should use the
fourth state to be more fair than the arbiter in the slides. Specifically, when there are no requests, the arbiter should remember the last client that was acknowledged. If, subsequently, two requests arrive at the same time, it should grant the one from the client that was not acknowledged last. With this change, you can no longer use the outputs as state variables. Instead, you need to define the grant outputs of the arbiter as a function of the state.
Complete the Verilog code with your description of the arbiter circuit using case
statements. Simulate the complete model to verify that your arbiter follows the rule outlined
above. In particular, look for transition of the request from 00 to 11 and check that the client
acknowledged after the requests go to 11 is not the one that was last acknowledged.
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