design a 7nm 6-t sram cell, with all transistors at the minimum gate length. the results are generated with the nominal model, and spice simulations. no layout needed. please include your spice netlist in your homework submission. a. the cell size is 111, characterize snm, rnm and wnm. characterize their values again at 112. b. under the size of 111, plot snm vs. vdd. if we define the data retention voltage (drv) as the value of vdd that snm