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A 5 MHz clock that generates a 0 to 5V pulse train with a 30% duty cycle is connected to input X of a two input OR gate that has a 20nS propagation delay. The clock also goes to an inverter with a 10ns propagation delay. The output of the inverter goes to the Y input of the OR gate.

a. Draw the circuit
b. Plot the output of the clock for two cycles. Show times and voltages.
c. Plot the output of the inverter in the same plot. Show times and voltages.
d. Plot the output of the OR gate in the same plot. Show times and voltages.

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Answer:

Timing Diagrams 15 pts. A 10 MHz clock that generates a 0 to 5V pulse train with a 30% duty cycle is connected to input X of a two input OR gate that has a 20nS propagation delay. The clock also goes to an inverter with a 10 ns propagation delay. The output of the inverter goes to the Y input of the OR gate. a) Draw the circuit. 2 pts. b) Plot the output of the clock for two cycles. Show times and voltages. 5 pts. c) On the same page as part (b) plot the output of the inverter. Show times and voltages. 3 pts. d) On the same page as parts (b & c) plot the output of the OR gate. Show times and voltages. 5 pts.

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